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Microtechnologist - Semiconductor TechnologyIndia |
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3 years experience |
Birthday:
Nationality:
Indian
20656152
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2007-09 – 2011-04
completed
Electronics and Communication Engineering
2017-10 – Till now
Layout of individual blocks in 22nm FDSOI. Layout of EM and ESD blocks in Top level. Physical verification in individual and top cells.
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To register2016-07 – 2017-10
Layout of individual blocks in 10nm and 14nm FinFET process. Physical Verification using Different tools. Filling of top blocks.
2015-04 – 2016-04
Responsibilities include working on the Layouts of individual blocks in 65nm and the top layout of that block with physical verifications.
Internship
2013-08-28 – 2013-12-17
IC design training in front end and back end. internship in same academy.
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Expert level knowledge in Layout tools such as Cadence Virtuoso, Intel FinFET tools. Strong knowledge in Analog and Mixed Signal Layout basics and fabrication processes. Strong knowledge in Physical verification tools with error debugging skills. Work Experience in different technological nods such as Intel 10nm, Intel 14nm, GF 22FDx, TSMC 45nm, TSMC 65nm, TSMC 130nm.
