09/2007 – 04/2011
abgeschlossen
Elektrotechnik
, Indien
Electronics and Communication Engineering
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Mikrotechnologe/-technologin - HalbleitertechnikIndien |
3 Jahre Erfahrung |
Geburtsdatum:
Staatsangehörigkeit:
indisch
20656152
09/2007 – 04/2011
abgeschlossen
Electronics and Communication Engineering
10/2017 – Bis heute
Layout of individual blocks in 22nm FDSOI. Layout of EM and ESD blocks in Top level. Physical verification in individual and top cells.
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Zur Registrierung07/2016 – 10/2017
Layout of individual blocks in 10nm and 14nm FinFET process. Physical Verification using Different tools. Filling of top blocks.
04/2015 – 04/2016
Responsibilities include working on the Layouts of individual blocks in 65nm and the top layout of that block with physical verifications.
Praktikum
28.08.2013 – 17.12.2013
IC design training in front end and back end. internship in same academy.
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Expert level knowledge in Layout tools such as Cadence Virtuoso, Intel FinFET tools. Strong knowledge in Analog and Mixed Signal Layout basics and fabrication processes. Strong knowledge in Physical verification tools with error debugging skills. Work Experience in different technological nods such as Intel 10nm, Intel 14nm, GF 22FDx, TSMC 45nm, TSMC 65nm, TSMC 130nm.